1. Field of the Invention
The present invention relates to a control circuit for an MPEG (Moving Picture Experts Group) system, and more particularly to a priority order processing circuit for an MPEG system adapted to determine the priority order of events generated from a multiprocessor of a decoding system utilizing MPEG1 and MPEG2 schemes while controlling operation of the system.
The present invention is based on Korean Patent Application No. 11950/1996, which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Generally, an MPEG system is a system for digitally converting audio or video information so that the information can be stored or transferred for the use or re-use thereof. In other words, such an MPEG system is adapted to provide for ease in handling audio or video information. To this end, the MPEG system essentially includes a coder/decoder for encoding audio or video information and for decoding coded information. An example of an MPEG system is illustrated in FIG. 1.
FIG. 1 is a block diagram illustrating the configuration of a conventional MPEG system. As shown in FIG. 1, the MPEG system includes a video decoder 14 for decoding a stream of coded video data, thereby outputting recovered video data, and a dynamic random access memory (DRAM) 15 (hereinafter, referred to as "memory") for storing the recovered video data output from the video decoder 14. A display controller 16 is also provided which serves to display the video data recovered by the video decoder 14 on a display unit (not shown). The MPEG system further includes a central processing unit (hereinafter, referred to as "CPU") 18 for controlling the entire operation of the MPEG system, and a main memory 20 for storing system information and accessing that stored information under control of the CPU 18.
In FIG. 1, the reference numeral 24 denotes a storage medium, in particular, a large-capacity storage medium such as a hard disk. Coded video or audio data streams are stored in the storage medium 24. The reference numeral 26 denotes an audio decoder which serves to decode coded audio data, thereby outputting recovered audio data. All the elements mentioned above are controlled by the CPU 18 to which those elements are coupled via a system bus 22.
The MPEG system having the configuration shown in FIG. 1 performs the following data processing under control of the CPU 18.
When the video decoder 14 operates under control of the CPU 18, it accesses coded bit stream data stored in the storage medium 24 and recovers video data from the accessed data. The video decoder 14 then controls the memory 15 to store the recovered video data. The recovered video data stored in memory 15 may be subsequently read for performing motion compensation or for display on a screen. For example, where motion compensation is necessary, the recovered video data stored in the memory 15 is read in accordance with a desired operation of the video decoder 14. For display on the screen, the video data, which has been recovered and motion compensated, is transferred to the display controller 16. The display controller 16 sends the recovered video data received from the video decoder 14 to a display unit (not shown) under control of the CPU 18 to display the recovered video. The audio decoder 26 also operates in a manner similar to the video decoder 14.
During the above-mentioned operation, the CPU 18 performs instructions for various jobs required for recovery of the video data. When the CPU 18 receives requests for jobs from data processors, such as the display controller 16 and audio decoder 26, it determines a priority order for processes respectively associated with those jobs requests. In accordance with the determined priority order, the CPU 18 performs allocation of authorities for jobs to execute a desired data processing operations. The CPU 18 also executes an operation for transferring system information, which is extracted from input data and stored in the main memory 20, at the request of the video decoder 12.
In the conventional MPEG system configured as shown in FIG. 1, however, the priority order for job requesting signals generated from various data processors is processed by an additional processor, namely, the CPU. As a result, it is necessary to execute a procedure which should use additional programming. In this case, there is an increase in costs because use of the CPU is expensive. This conventional MPEG system also has a problem in that the processing speed is low. This is because the priority order for job request signals generated from data processors is determined by the CPU which operates in accordance with a program.